Santiago Delgado

Electrical Engineering · Minor in Robotics · UTEP

Santiago Delgado

Built on the bench.

I design circuits, write the firmware that runs on them, and test them until they work. Looking for embedded systems, automotive, and hardware engineering roles.

See the work Résumé (PDF)
B.S. EE · Dec 2027 Researcher · PRES Lab Treasurer · IEEE English / Spanish

Get the highlights.

0.93%
grid forecast error1
Research
5 s
link-loss detection
Embedded
4
FSM states on an FPGA
Digital design
0.5–100 Hz
ECG band kept
Analog

Research · Power and Renewable Energy Systems Lab

Forecasting the grid.

I applied K-means clustering and 4 forecasting models to ERCOT load data, reaching 0.93% MAPE and beating linear regression by 77%. Now I model a 39-bus grid to see how data centers push voltage toward collapse.

May 2026 – PresentAdvisor: Dr. Paras MandalWith Travis Newbolt
COURI 2026 research poster: Comparative Analysis of Machine Learning Algorithms for Load Demand Forecasting
COURI 2026 poster · tap to open full size

Forecast error

0.93%

MAPE for the neural network.1

Presented to

120

attendees at COURI 2026. Led to 2 project proposals.

Grid model

39-bus

Built and validated in PyPSA and pandapower.

Model comparison · from my MATLAB results

Bar charts of MAE, RMSE and MAPE for ANN, decision tree, SVM and linear regression; the ANN has the lowest error and linear regression the highest
The neural network (ANN) had the lowest MAE, RMSE, and MAPE of the four models.1
Santiago presenting his research poster at COURI 2026
Presenting at COURI 2026

What I did

  • Grouped ERCOT hourly load with seasonal K-means to isolate high-demand summer hours.
  • Trained a 10-neuron feedforward network and benchmarked it against linear regression, decision trees, and an SVM.
  • Built a 39-bus model in PyPSA and pandapower as a baseline for a voltage-collapse risk study.
  • Generated a year of data-center load profiles sized at 25–30% of system load.
MATLABPythonPyPSApandapowerNeural networks
View full poster

Embedded systems · Seizure detection

Two boards.
One reliable link.

A 2-module seizure-alert system on MSP432 microcontrollers. I built Module B, which takes motion classifications over a checksummed UART link and turns them into timed alerts and caregiver controls.

Apr – May 2026Team of 2 · Module A by Daniel MendozaEmbedded C · Code Composer Studio
Module A and Module B on MSP432 boards with LCDs
Bench build · Module A (top), Module B (bottom)

System view · my module in copper

Module A Motion sensing UART frames new threshold XOR checksum · 5 s timeout Module B MSP432 · my build IRQ UART RX/TX 256-byte TX buffer event timing Caregiver buttons + ADC arm · ack · reset · test · 3 levels 16×2 LCD 4-digit timer Visual alerts Servo 5-event log
2
MSP432 boards on one serial link
5 s
link-loss timeout
3
ADC sensitivity levels
256-byte
interrupt-driven TX buffer
5
caregiver controls incl. self-test

What I did

  • Wrote a framed UART protocol with XOR checksums and interrupt-driven receive and transmit.
  • Added a 5-second timeout so Module B flags a lost link instead of failing silently.
  • Read a 14-bit ADC to set 3 sensitivity levels and sent new thresholds back to Module A.
  • Drove a 16×2 LCD, a multiplexed 4-digit timer, servo pulses, and a 5-event circular log.
  • Built arm, disarm, acknowledge, reset, and self-test controls for the caregiver.2
Embedded CUARTADCInterruptsSysTickHW/SW integration

Digital design · Verilog FSM

Press. Wait. Walk.

I designed and simulated a 4-state finite-state machine in Verilog for a 2-direction traffic intersection, then ran it on a Basys-3 FPGA using only the board's LEDs, button, and 4-digit display.

Oct – Dec 2025Solo projectXilinx Vivado · ModelSim · XDC constraints

Try it · model of the light sequence

Vehicles
STOP
WALK
Pedestrians

4-digit display

8888

Idle. Press the button to cross.

The four states

  1. IdlePedestrian STOP on, waiting for a request.
  2. YellowVehicles slow down while STOP flashes, about 3 s.
  3. Red / WalkPedestrians cross with a 10 s countdown.
  4. ClearCountdown ends, STOP returns, back to idle.
Digilent Basys-3 FPGA board
Basys-3 · no external parts

What I did

  • Designed a 4-state FSM in Verilog with timed transitions and simulated it in ModelSim.
  • Ran a 10-second walk countdown on the board's 4-digit display.
  • Debugged synthesis errors and fixed timing constraints in the XDC file in Vivado.
VerilogFSM designVivadoModelSimFPGA I/O

Software · C programming

Memory, managed.

A command-line inventory and checkout app in C that sizes its own arrays at runtime, sorts and filters products, and saves everything to a binary file.

Nov – Dec 2025Solo projectC · structs · malloc / free · binary I/O

Program structure

Menu 13 options Inventory array 8 fields per product sort by category or price Shopping cart array dynamically allocated quantities for receipt Binary file save / load on exit Receipt totals + 10% off free() on exit

Menu

13

options: add, delete, filter, sort, cart, receipt, save, load and more.

Product record

8

fields per item, including category, source, price, stock, and serial number.

Discount

10%

applied on the receipt to flagged products.

What I did

  • Stored inventory and cart in dynamically allocated arrays instead of fixed-size tables.
  • Wrote add, delete, category filter, and sort by category or price.
  • Added binary save and load so inventory persists between runs, and freed all memory on exit.
CMemory managementFile I/OData structuresSorting

Analog electronics · ECG

From millivolts to a clean heartbeat.

A 3-stage analog circuit picks up a heart signal with an instrumentation amplifier and uses op-amp filters to keep the 0.5–100 Hz band, then the output is converted to digital for processing.

Aug – Oct 2025Team of 2 · with Leila ArmstrongMy part: stage calculations, part values, assembly, filtering
CH1 · electrode input (mV, noisy) CH2 · after HPF → in-amp → LPF

Animation of what each stage does. The real capture is below.

Stage 1

High-pass filter

0.5 Hz cutoff removes slow drift.

Stage 2

Instrumentation amplifier

Boosts the tiny difference between electrodes.

Stage 3

Low-pass filter

100 Hz cutoff removes high-frequency noise.

Output

To digital

Converted for processing and checked on the scope.

ECG circuit on a breadboard
Breadboard build3
Oscilloscope showing the circuit's output trace
Output on the oscilloscope

What I did

  • Calculated the amplifier stages and selected component values.
  • Assembled the instrumentation amplifier stages on a breadboard.
  • Added high-pass input and low-pass output filters to keep 0.5–100 Hz.
  • Converted the analog output to digital for processing.
Op-amp designFilter designBiosignalsOscilloscope
Original circuit photo

Experience and leadership

Leads in the lab.
And off it.

May 2026 – Present

Undergraduate Researcher

Power and Renewable Energy Systems Lab, UTEP

Load forecasting and grid stability research.

Aug 2024 – Apr 2026

Service Manager

Great American Steakhouse

Supervised a 20-person staff across 3 shifts, serving 1,000+ customers a week.

Aug 2024 – Dec 2027

B.S. Electrical Engineering

UTEP · Minor in Robotics · GPA 3.16

Study abroad in Spain and Japan.

Apr 2026 – Present

Treasurer

IEEE

Manage the budget, expenses, and records, and fund events and workshops.

Apr 2026 – Present

External Affairs Officer

IEEE Robotics and Automation Society

Main contact for sponsors, partners, and other chapters.

Apr 2024 – Present

Operations Chair

Society of Hispanic Professional Engineers

Rooms, food, and logistics that keep events on schedule.

Tech specs.

Languages

  • C
  • Embedded C++
  • MATLAB
  • Python
  • Verilog

Embedded

  • UARTframed, checksummed, interrupt-driven
  • ADC14-bit, sensitivity control
  • PWM
  • TimersSysTick

Hardware

  • Analog circuit design
  • Digital logic design
  • Hardware debugging
  • Oscilloscope

Tools

  • Code Composer Studio
  • Xilinx Vivado
  • ModelSim
  • PyPSA · pandapower
  • VS Code
  • Microsoft Office

Coursework

  • Microprocessor Systems
  • Digital Logic Design
  • Software Design
  • Operating System Design

Open to Summer 2027 internships and co-ops

Let's build something.

Embedded, automotive, and hardware teams especially.

Email

santdelg5995@gmail.com

Phone

915-494-8460

LinkedIn

linkedin.com/in/santiago-d

Open profile
Résumé (PDF) Portfolio (PDF)
Source